Embodiments of the present invention relate to analog circuits, and more particularly, to analog circuits for providing waveform parameters.
Mixed signal circuits often evaluate several waveform parameters, such as, for example, the maximum, minimum, or average values, or the root-mean-square value. These waveform parameters are often evaluated in the analog domain because they are needed prior to A/D (analog-to-digital) conversion.
Typically, passive networks in combination with diodes (or diode-configured transistors) have been used to evaluate waveform parameters. For example, a typical averaging circuit is shown in FIG. 1, comprising resistor 102 and capacitor 104. A peak detector circuit is shown in FIG. 2, comprising diode 202 and capacitor 204. A nMOSFET (n-Metal-Oxide-Semiconductor-Field-Effect-Transistor) averaging detector is shown in FIG. 3, comprising nMOSFET 302 and parasitic capacitor 304. The gate of nMOSFET 302 is biased to a bias voltage Vbias. In FIG. 3, the output network is indicated explicitly by Output Network block 306, but it is implicit in the other figures.
Another common task in analog signal processing is the extraction of a waveform""s DC (Direct Current) offset. DC offset extraction is often required for A/D conversion. Prior art DC offset extraction circuits may use passive networks. For example, the circuit of FIG. 1 may be utilized to provide a DC offset. An example of a typical prior art DC offset correction circuit utilizing an active device is shown in FIG. 4, where nMOSFET 402 is biased to a bias voltage Vbias. nMOSFET 402 and capacitor 404 provide an averaging circuit to provide a DC offset. DC Offset Correction block 406 provides the DC offset to Input Stage 410, where it is subtracted from the input signal after passing through Input Stage 408.
Prior art circuits such as FIGS. 1 and 2 require components such as resistors or diodes, and may not be compatible with some low voltage CMOS (Complementary-Metal-Oxide-Semiconductor) process technology. Prior art circuits such as FIGS. 3 and 4 require a bias voltage to bias nMOSFETs, adding to circuit complexity, and relatively large capacitances and low bias voltages may be needed to reject ripples below 1 KHz. It is advantageous to provide analog parameter evaluation circuits that take advantage of sub-micron (e.g., less than 0.13 microns) CMOS process technology without requiring diodes and resistors, and without the need for large capacitances and a separate bias voltage.